A Modified ecimation ilter esign for Oversampled Sigma elta A/ Converters

Author

Lei, Chen ; Yuanfu, Zhao ; Gao Deyuan ; Wu, Wen ; Zongmin, Wang ; Xiaofei, Zhu ; Heping, Pen

Author_Institution

Aviation Mcroelectronic Center, Northwestern Polytech. Univ., Xi´´an

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

294

Lastpage

297

Abstract

The paper presents a novel lower power polyphase transformable stage nonrecursive comb (PTSNC) filter architecture considering the area and power consumption, which is very suitable for high-order oversampled sigma delta A/D converters. The proposed decimation filter has 1/3 less hardware and power compared to conventional non-recursive decimation filters when the filter was implemented using 0.6-mum CMOS standard when the circuit work clock was 100MHz

Keywords

CMOS digital integrated circuits; clocks; comb filters; digital filters; integrated circuit design; low-power electronics; sigma-delta modulation; 0.6 micron; 100 MHz; CMOS technology; circuit work clock; decimation filter design; low power filter; polyphase transformable stage nonrecursive comb filter architecture; sigma delta A-D converters; Delta-sigma modulation; Energy consumption; Finite impulse response filter; Frequency; Hardware; IIR filters; Noise reduction; Quantization; Read only memory; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611308

Filename

1611308