DocumentCode
453657
Title
An efficient equalizer for DVB-T receivers
Author
Zhi, Liu ; Zhou, Jiang ; Jing, Wang ; Chenling, Huang ; Xiaoyang, Zeng
Author_Institution
ASIC & Syst. State Key Lab, Fudan Univ., Shanghai
Volume
1
fYear
2005
fDate
24-0 Oct. 2005
Firstpage
236
Lastpage
239
Abstract
The equalizer is one of the core components of DVB-T receivers. In this paper, we propose a robust and low complexity equalizer that includes a 2D Wiener filter estimation unit and an equalization unit. The VLSI architecture of it is also given. Simulation results show that the proposed low complexity equalizer has high performance in static or low-speed cases and it will find its use in many wireless applications
Keywords
VLSI; Wiener filters; digital video broadcasting; equalisers; television receivers; 2D Wiener filter estimation unit; DVB-T receivers; VLSI architecture; equalization unit; low complexity equalizer; Equalizers; Frequency domain analysis; Frequency estimation; Frequency response; High level synthesis; Interpolation; Nonlinear filters; Scattering; Very large scale integration; Wiener filter; V SI; VB-T; equalizer;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location
Shanghai
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611309
Filename
1611309
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