Reconfigurable VLSI architecture for VBSME in MPEG-4 AVC/H.264

Author

Wei, Cao ; Gang, Mao Zhi

Author_Institution

Microelectron. Center, Harbin Inst. of Technol.

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

265

Lastpage

269

Abstract

VBSME is adopted in the MPEG-4 AVC/H.264 standard. In this paper, we proposed a new reconfigurable VLSI architecture for VBSME with 3 levels of computing complexity to support FS and fast search area sub-sampling ME algorithms. The architecture can reuse the smaller blocks´ SADs to calculate 41 motion vectors of a 16times16 block in parallel. Our design was implemented with 0.25mum CMOS technology. Under a clock frequency of 52Mhz, the architecture allows the real-time processing of 352times288 (or 720times576) at 30fps with FS (or fast algorithms) in a search range [-16, +15]

Keywords

CMOS integrated circuits; VLSI; computational complexity; digital signal processing chips; parallel processing; reconfigurable architectures; video coding; 0.25 micron; 52 MHz; CMOS technology; H.264 standard; MPEG-4 AVC standard; VBSME; fast search area sub-sampling ME algorithm; real-time processing; reconfigurable VLSI architecture; Automatic voltage control; CMOS technology; Computer architecture; MPEG 4 Standard; Microelectronics; Motion estimation; Registers; Switches; Very large scale integration; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611316

Filename

1611316