Title :
A direct conversion WLAN receiver
Author :
Wang, Jingguang ; Wang, Jinju ; Huang, Yumei ; Shen, Weilun ; Yi, Xiaofeng ; Hong, Zhiliang
Author_Institution :
State Key Lab of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
A direct conversion receiver for WLAN 802.11b is presented in 0.18μm CMOS technology. It contains a complete receiver chain with low noise amplifier, I/Q mixer, programmable gain amplifier and base band filter. A 4.8GHz divider is used to generate 2.4GHz quadrature clock for I/Q mixer. The reception path is dc coupled and a feed back low pass filter is added to reduce the dc-offset and 1/f noise. The noise figure of receiver is 5.2dB, the IIP3 is -14.5dBm at high gain setting. With the supply voltage of 1.8V, the over all power consummation is about 100mW. The chip area with pads is 2.6mm×2.5mm.
Keywords :
1/f noise; CMOS integrated circuits; MMIC; dividing circuits; low noise amplifiers; mixers (circuits); radio receivers; wireless LAN; 0.18 micron; 1-f noise; 1.8 V; 2.4 GHz; 2.5 mm; 2.6 mm; 4.8 GHz; 5.2 dB; CMOS technology; I-Q mixer; WLAN 802.11b; base band filter; dc-offset; direct conversion receiver; feedback low pass filter; low noise amplifier; programmable gain amplifier; quadrature clock; Band pass filters; CMOS technology; Clocks; Feeds; Low pass filters; Low-noise amplifiers; Noise figure; Noise reduction; Voltage; Wireless LAN; 1/f noise; CMOS; WLAN; base band filter; dc-offset; direct conversion; low noise amplifier; mixer; programmable gain amplifier; receiver;
Conference_Titel :
ASIC, 2005. ASICON 2005. 6th International Conference On
Print_ISBN :
0-7803-9210-8
DOI :
10.1109/ICASIC.2005.1611341
