DocumentCode
453677
Title
A 1.8V transmitter for 10/100 Mbps Ethernet physical layer
Author
Cheng, Tao ; Li, Yang ; Ning, Li ; Ping, Lu ; Junyan, Ren ; Lian, Li
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai
Volume
1
fYear
2005
fDate
24-0 Oct. 2005
Firstpage
415
Lastpage
418
Abstract
A 0.18 mum 1.8 V CMOS transmitter for 10/100Mbps Ethernet physical layer standards is described in this paper. The circuit is substantively a current-steering digital-to-analog converter with 5-bit resolution, 125MHz sample rate and 4ns transition time. A novel latch circuit is designed, as well as a structure is provided to realize the accurate rise/fall time control of waveform
Keywords
CMOS logic circuits; digital-analogue conversion; flip-flops; local area networks; transmitters; 0.18 micron; 1.8 V; 10 Mbit/s; 100 Mbit/s; 125 MHz; 4 ns; 5 bit; CMOS transmitter; Ethernet physical layer; current steering; current-steering digital-to-analog converter; Analog-digital conversion; Circuits; Clocks; Ethernet networks; Frequency synthesizers; Laboratories; Latches; Physical layer; Switches; Transmitters; 1265H; 1280; 1285; 1290B; Current-Steering; Digital-to-Analog; Ethernet; Glitch EEACC: 1205; Transmitter;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location
Shanghai
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611349
Filename
1611349
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