A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap

Author

Tseng, Tsu-Wei ; Li, Jin-Fu ; Chang, Da-Ming

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli

Volume

1

fYear

2006

fDate

6-10 March 2006

Abstract

Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-on-chips (SOCs). To increase the utilization of memory redundancy, the BISR technique usually needs to perform built-in redundancy-analysis (BIRA) algorithm for redundancy allocation. This paper presents an efficient BIRA scheme for embedded memory repair. The BIRA scheme executes the 2D redundancy allocation based on the ID local bitmap. This enables that the BIRA circuitry can be implemented with low area cost. Also, the BIRA algorithm can provide good repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). Experimental results show that the repair rate of the proposed BIRA scheme approximates to that of the optimal scheme for the memories with different fault distributions. Also, the ratio of the analysis time to the test time is small

Keywords

built-in self test; fault diagnosis; integrated circuit reliability; random-access storage; redundancy; system-on-chip; 1D local bitmap; BIRA algorithm; RAM; built-in redundancy-analysis; built-in self-repair; fault distribution; redundancy allocation; system-on-chip; Algorithm design and analysis; Circuit faults; Costs; Hardware; Laboratories; Random access memory; Read-write memory; Redundancy; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings

Conference_Location

Munich

Print_ISBN

3-9810801-1-4

Type

conf

DOI

10.1109/DATE.2006.243969

Filename

1656845