Designing signal processing systems for FPGAs

Software tools have helped the designer develop and simulate their designs, thus helping to improve productivity. One commonly used sub-function of these high-performance DSP systems is sample rate conversion, this function could be implemented into a design with greater ease and at a faster rate if the building blocks such as up/down sampling, clock domains, FIFOs, and clock enables were pre-verified and available to just drop into a design. Another factor is the increasingly aggressive demands being placed on performance and productivity. Therefore designers now have to find new ways to speed up design development, and new ways to improve the methodology of getting designs to product. A tool was needed that would allow the designer to continue working in a familiar environment, but which allowed designs to be verified in "hardware in the loop", meaning that the designer could run their design on any board fitted with the appropriate FPGA. To resolve the "getting to product" challenge there was a need for a tool that could link the environment provided by the Mathworks tools to the hardware description language (HDL) environment utilised by the hardware people