• DocumentCode
    454431
  • Title

    Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications

  • Author

    Bartzas, Alexandros ; Mamagkakis, Stylianos ; Pouiklis, Georgios ; Atienza, David ; Catthoor, Francky ; Soudris, Dimitrios ; Thanailakis, Antonios

  • Author_Institution
    VLSI Design & Testing Center, Democritus Univ., Xanthi
  • Volume
    1
  • fYear
    2006
  • fDate
    6-10 March 2006
  • Abstract
    Network applications are becoming increasingly popular in the embedded systems domain requiring high performance, which leads to high energy consumption. In networks is observed that due to their inherent dynamic nature the dynamic memory subsystem is a main contributor to the overall energy consumption and performance. This paper presents a new systematic methodology, generating performance-energy trade-offs by implementing dynamic data types (DDTs), targeting network applications. The proposed methodology consists of: (i) the application-level DDT exploration; (ii) the network-level DDT exploration; and (iii) the Pareto-level DDT exploration. The methodology, supported by an automated tool, offers the designer a set of optimal dynamic data type design solutions. The effectiveness of the proposed methodology is tested on four representative real-life case studies. By applying the second step, it is proved that energy savings up to 80% and performance improvement up to 22% (compared to the original implementations of the benchmarks) can be achieved. Additional energy and performance gains can be achieved and a wide range of possible trade-offs among our Pareto-optimal design choices are obtained, by applying the third step. We achieved up to 93% reduction in energy consumption and up to 48% increase in performance
  • Keywords
    Pareto optimisation; circuit optimisation; embedded systems; integrated circuit design; integrated memory circuits; logic design; Pareto-level DDT exploration; Pareto-optimal design; application-level DDT exploration; dynamic data type refinement; dynamic memory subsystem; embedded systems; network applications; network-level DDT exploration; performance-energy design exploration; Benchmark testing; Embedded system; Energy consumption; Large scale integration; Performance evaluation; Performance gain; Runtime; Telecommunication traffic; Very large scale integration; Wireless networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
  • Conference_Location
    Munich
  • Print_ISBN
    3-9810801-1-4
  • Type

    conf

  • DOI
    10.1109/DATE.2006.244093
  • Filename
    1656987