• DocumentCode
    454507
  • Title

    Test Compaction for Transition Faults under Transparent-Scan

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M.

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., W. Lafayette, IN
  • Volume
    1
  • fYear
    2006
  • fDate
    6-10 March 2006
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application time for stuck-at faults. We show that similar advantages exist when considering transition faults. We first show that a test sequence under the transparent-scan approach can imitate the application of broadside tests for transition faults. Test compaction can proceed similar to stuck-at faults by omitting test vectors from the test sequence. A new approach for enhancing test compaction is also described, whereby additional broadside tests are embedded in the transparent-scan sequence without increasing its length or reducing its fault coverage
  • Keywords
    automatic test pattern generation; fault simulation; logic design; scan circuits; stuck-at faults; test compaction; test generation; transition faults; transparent-scan; Application software; Circuit faults; Circuit testing; Cities and towns; Clocks; Compaction; Flexible printed circuits; Flip-flops; Interleaved codes; Sequential analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
  • Conference_Location
    Munich
  • Print_ISBN
    3-9810801-1-4
  • Type

    conf

  • DOI
    10.1109/DATE.2006.244098
  • Filename
    1657089