Equalizing Sampling Rate Converter for Storage Systems

Data receivers for storage systems normally operate at a fixed sampling rate 1/T_S that is asynchronous to the baud rate 1/T. A sampling-rate converter (SRC) serves to convert the incoming signal from the asynchronous to the synchronous clock domain. These receivers also contain an equalizer that serves to suppress intersymbol interference and noise. To limit receiver complexity, equalization burden can be shifted towards the SRC. This possibility is not exploited in any existing SRC. This paper presents SRC design methods that combine group delay flatness and out-of-band rejection criteria with the minimum mean square error equalization criterion. Numerical examples for an idealized optical recording channel validate the design methods