The Hardware Implementation of A Multi-resolution Combined Fuzzy Min-Max Classifier Chip

This paper presents the design and implementation of a multi-resolution combined fuzzy neural network classifier. To improve classification speed, a parallel structure is developed for the classifier. The classifier presented consists of 4 parallel classification logic units, each of which has the same structure and functions, so that the classification logic units can operate classification simultaneously and obtain results at the same time. The classifier is realized using field programmable gate array (FPGA) and application specific integrated circuit (ASIC). Test results show that the maximal operation frequency is 100 MHz and the chip can be cascaded to achieve high speed classification