Title :
Self-Adaptive Network-on-Chip Interface
Author :
Dafali, Rachid ; Diguet, Jean-Philippe ; Creput, Jean-Charles
Author_Institution :
Lab.-STICC, Univ. de Bretagne Sud, Lorient, France
Abstract :
This letter presents an original approach of bandwidth-oriented self-adaptivity in the domain of network-on-chip, where reconfiguration is handled by network interfaces offering traffic with guarantee of service. Reconfiguration is first based on multiple first-in-first-outs (FIFOs) with variables bounds and implemented in a single dual-port memory with a dedicated controller. Secondly, it relies on multiple and compliant TDMA tables based on a new heuristic for path computation. Combination of both techniques provide significant bandwidth improvement with a negligible resource overhead. The proposed solution is demonstrated with cycle-accurate VHDL simulation and FPGA implementation for synthetic and image processing applications.
Keywords :
field programmable gate arrays; hardware description languages; image processing; network interfaces; network-on-chip; reconfigurable architectures; time division multiple access; FIFO; FPGA implementation; bandwidth improvement; compliant TDMA tables; cycle-accurate VHDL simulation; image processing applications; multiple TDMA tables; multiple first-in-first-outs; network interfaces; path computation; resource overhead; self-adaptive network-on-chip interface; single dual-port memory; synthetic applications; variable bounds; Computer architecture; Network-on-chip; Ports (Computers); Program processors; Reconfigurable architectures; Time division multiple access; Topology; Dynamic reconfiguration; TDMA; first-in–first-out (FIFO); network-interfaces; reconfigurable network-on-chip (RNoC); self-adaptivity;
Journal_Title :
Embedded Systems Letters, IEEE
DOI :
10.1109/LES.2013.2285175