Title :
Deep Depletion SOI Power Devices
Author_Institution :
Dept. of Electron. & Telecommun. Eng. Electron. & Telecommun. Eng., Napoli Univ.
Abstract :
The paper presents an innovative design concept for SOI lateral power devices that exploits the deep depletion of the substrate to dynamically increase the voltage rating of SOI devices. Numerical simulations of the device and experimental results demonstrate that the proposed physical effect is a viable way to design a whole new class of lateral power devices
Keywords :
power MOSFET; semiconductor device breakdown; silicon-on-insulator; deep depletion; power semiconductor devices; semiconductor device breakdown; silicon-on-insulator; Consumer electronics; Epitaxial layers; Isolation technology; Logic design; Logic devices; Low voltage; Power electronics; Power integrated circuits; Silicon on insulator technology; Thermal resistance; Power MOSFETs; power semiconductor devices; semiconductor device breakdown; silicon on insulator (SOI) technology; switching transient;
Conference_Titel :
International Semiconductor Conference, 2006
Conference_Location :
Sinaia
Print_ISBN :
1-4244-0109-7
DOI :
10.1109/SMICND.2006.283922
