Bit-Level Parallel Array Algorithms of Vector-Vector and Matrix-Matrix Multiplication

Based on Horner´ rule and Baugh-Wooley algorithm, this paper presents two novel bit-level parallel array algorithms of 2´s complement multiplication, and the algorithms have been mapped to systolic arrays by using linear mapping techniques. We propose two efficient systolic arrays of multiply and accumulate (MAC) operation and we also describe the vector-vector and matrix-matrix multiplication that can be efficiently implemented by using the MAC arrays. The two systolic arrays have high performance (low time complexity, space complexity and latency) and consume smaller gate-area in comparison to other architectures. It is suitable for VLSI implementation for its regularity and modularity