DocumentCode :
460612
Title :
Sizing Buffers for Pipelined Forwarding Engine
Author :
Li, Yufeng ; Yi, Peng ; Qiu, Han ; Lan, Julong
Author_Institution :
Nat. Digital Switching Syst. Eng. & Technol. Res. Center, Zhengzhou
Volume :
3
fYear :
2006
fDate :
25-28 June 2006
Firstpage :
1681
Lastpage :
1685
Abstract :
Packet buffers in routers constitute a central element of packet networks. Selecting appropriate buffer size is an important and open research problem. This paper aims to size buffers for forwarding engine known as one of the main parts of a router. First, a high-speed pipeline which is designed for forwarding engine is presented, and its memory analysis model is also given, then, the memory requirement of the forwarding engine is analyzed under two conditions: the forwarding rate is not less than and less than the input rate. Our analysis results and experiment both show that, the proposed forwarding pipeline is of high performance, and just one pipeline can deal with the data transfer rate of 20 Gb/s or even higher; the pipelined forwarding engine only need to buffer a several packets, then the loss rate will be an acceptable value or even zero, further increasing the buffer size will have little effect on reducing the loss rate
Keywords :
Internet; buffer storage; packet switching; pipeline processing; telecommunication network routing; Internet routers; data transfer rate; high-speed pipelined forwarding engine; memory analysis model; packet buffers; packet switching networks; Delay effects; Field programmable gate arrays; Jitter; Performance analysis; Performance loss; Pipelines; Routing; Search engines; Switching systems; Systems engineering and theory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Circuits and Systems Proceedings, 2006 International Conference on
Conference_Location :
Guilin
Print_ISBN :
0-7803-9584-0
Electronic_ISBN :
0-7803-9585-9
Type :
conf
DOI :
10.1109/ICCCAS.2006.284997
Filename :
4064223
Link To Document :
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