Design, Implementation and Testing of the Controller for the Terabit Packet Switch

Author

Petrovic, Milos ; Blagojevic, Milos ; Smiljanic, Aleksandra ; Jokovic, Vladimir

Author_Institution

Belgrade Univ.

Volume

3

fYear

2006

fDate

25-28 June 2006

Firstpage

1701

Lastpage

1705

Abstract

The sequential greedy scheduling (SGS) is a scalable algorithm that provides non-blocking in high-capacity packet switches. We implemented the SGS scheduler in the FPGA device, and examined its scalability and speed. Then, we developed the software for design testing. Our testing software confirms the correct functioning of the scheduler. Both, the scheduler implementation, and the testing software are presented in this paper

Keywords

field programmable gate arrays; logic CAD; logic testing; microcontrollers; network-on-chip; packet switching; processor scheduling; sequential switching; FPGA device; high-capacity terabit packet switch; sequential greedy scheduling controller design; sequential greedy scheduling controller implementation; sequential greedy scheduling controller testing; Computer architecture; Cyclones; Field programmable gate arrays; Memory management; Packet switching; Pipelines; Processor scheduling; Scheduling algorithm; Software testing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems Proceedings, 2006 International Conference on

Conference_Location

Guilin

Print_ISBN

0-7803-9584-0

Electronic_ISBN

0-7803-9585-9

Type

conf

DOI

10.1109/ICCCAS.2006.285001

Filename

4064227