A CMOS Front-end Circuit for SONET OC-96 Receiver

Author

Jinbin, Liu ; Ming, Gu ; Hongda, Chen ; Peng, Gao

Author_Institution

State Key Lab. on Integrated Optoelectron. Inst. of Semicond., Chinese Acad. of Sci., Beijing

Volume

3

fYear

2006

fDate

38869

Firstpage

1961

Lastpage

1965

Abstract

An optical receiver front-end for SONET OC-96 receivers was analyzed and designed in 0.18 mum CMOS process. It consists of a transimpedance amplifier (TIA) and a limiting amplifier (LA). The TIA takes a fully differential configuration, and regulated cascode (RGC) input stage is implemented. The LA was realized by five cascaded identical gain stages with active inductor load. The TIA achieved 4.2 GHz bandwidth for 0.5 pF photodiode (PD) capacitance and 1.2 kOmega transimpedance gain. The LA achieved 5.4 GHz bandwidth and 29 dB voltage gain. The optical sensitivity is -19 dBm at 5-Gb/s for a bit-error rate of 10^-12, and it dissipates 45.5 mW for 1.8 V supply

Keywords

CMOS integrated circuits; SONET; differential amplifiers; error statistics; integrated optoelectronics; optical receivers; photodiodes; 0.5 pF; 1.8 V; 29 dB; 4.2 GHz; 45.5 mW; 5 Gbit/s; 5.4 GHz; CMOS front-end circuit; SONET OC-96 receiver; active inductor load; bit-error rate; cascaded identical gain stages; cascode input stage; differential configuration; limiting amplifier; optical receiver; optical sensitivity; photodiode; transimpedance amplifier; Active inductors; Bandwidth; CMOS process; Capacitance; Circuits; Optical amplifiers; Optical design; Optical receivers; Photodiodes; SONET;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems Proceedings, 2006 International Conference on

Conference_Location

Guilin

Print_ISBN

0-7803-9584-0

Electronic_ISBN

0-7803-9585-9

Type

conf

DOI

10.1109/ICCCAS.2006.285058

Filename

4064284