A ΣΔ Fractional-N PLL with Multiple Charge Pumps and Capacitance Scaling Scheme

A novel SigmaDelta fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status for fast locking and fractional spur suppressing while keeping LF capacitors small enough to be integrated into a single PLL chip. It has been simulated by HSPICE in a CMOS 0.35mum process, and shows that locking time is less than 8mus with the small size of LF capacitors, 200pF and 17pF, and 2.8KOmega resistor