DocumentCode :
460929
Title :
Power-smart system-on-chip architecture for embedded cryptosystems
Author :
Vahedi, H. ; Gregori, S. ; Zhanrong, Y. ; Muresan, R.
Author_Institution :
University of Guelph, Guelph, Canada
fYear :
2005
fDate :
Sept. 2005
Firstpage :
184
Lastpage :
189
Abstract :
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provides support for masking these channels by controlling, in real-time, the power and the current consumption of a system to predefined programmable values. The main components of the architecture are a processor core, a current sensor module, a dynamically controlled power supply module, a clock frequency control module, and a current injection module. Real-time current measurements and power-aware voltage control are used in closed loop architecture to regulate and minimize the total power consumption of the system. Simulation results show that the current consumption of the system can be regulated to a reference level with reduced power-to-security trade off (power overhead less than 12% of the total power).
Keywords :
Clocks; Control systems; Cryptography; Current measurement; Frequency control; Power supplies; Real time systems; System-on-a-chip; Timing; Voltage control; DES; current flattening in hardware; power analysis attack resistant architecture; power-smart system-on-chip; voltage scaling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Hardware/Software Codesign and System Synthesis, 2005. CODES+ISSS '05. Third IEEE/ACM/IFIP International Conference on
Conference_Location :
Jersey City, NJ, USA
Print_ISBN :
1-59593-161-9
Type :
conf
DOI :
10.1145/1084834.1084883
Filename :
4076334
Link To Document :
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