DocumentCode
460940
Title
Automatic network generation for system-on-chip communication design
Author
Gerstlauer, Andreas ; Gajski, Daniel D. ; Dömer, Rainer ; Shin, Dongwan
Author_Institution
University of California, Irvine, CA
fYear
2005
fDate
Sept. 2005
Firstpage
255
Lastpage
260
Abstract
With growing system complexities, system-level communication design is becoming increasingly important and advanced, network-oriented communication architectures become necessary. In this paper, we extend previous work on automatic communication refinement to support non-traditional, network-oriented architectures beyond a single bus. From an abstract description of the desired communication channels, the refinement tools automatically generate executable models and implementations of the system communication at various levels of abstraction. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness of the approach for rapid, early communication design space exploration.
Keywords
Computational modeling; Computer networks; Computer simulation; Embedded computing; Message passing; Network topology; Permission; System-level design; System-on-a-chip; Time to market; communication synthesis; system level design;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware/Software Codesign and System Synthesis, 2005. CODES+ISSS '05. Third IEEE/ACM/IFIP International Conference on
Conference_Location
Jersey City, NJ, USA
Print_ISBN
1-59593-161-9
Type
conf
DOI
10.1145/1084834.1084899
Filename
4076346
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