A Custom-made Algorithm-Specific Processor for Model Predictive Control

Author

Vouzis, P.D. ; Bleris, L.G. ; Arnold, M.G. ; Kothare, M.V.

Author_Institution

Dept. of Comput. Sci. & Eng., Lehigh Univ.

Volume

1

fYear

2006

fDate

9-13 July 2006

Firstpage

228

Lastpage

233

Abstract

This paper presents an algorithm-specific processor for embedded model predictive control (MPC). After analyzing the computational cost of MPC, via profiling, we observe that the optimizations associated with MPC are dominated by operations on real matrices. To overcome this bottleneck we propose connecting a limited resource host processor with an algorithm-specific matrix processor, whose architecture is described. The matrix processor uses a 16-bit logarithmic number system (LNS) arithmetic unit to carry out the required arithmetic operations. The proposed architecture is implemented using a hardware description language (HDL) and subsequently it is synthesized and emulated on a field programmable gate array (FPGA). The timing and area cost results are presented and analyzed

Keywords

control system CAD; field programmable gate arrays; hardware description languages; mathematics computing; optimisation; predictive control; process algebra; 16-bit logarithmic number system arithmetic unit; FPGA; HDL; algorithm-specific matrix processor; computational cost; custom-made algorithm-specific processor; field programmable gate array; hardware description language; host processor; model predictive control; profiling; Arithmetic; Computational efficiency; Computer architecture; Costs; Field programmable gate arrays; Hardware design languages; Joining processes; Predictive control; Predictive models; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics, 2006 IEEE International Symposium on

Conference_Location

Montreal, Que.

Print_ISBN

1-4244-0496-7

Type

conf

DOI

10.1109/ISIE.2006.295597

Filename

4077928