Designing an HMAC-Hash Unit on FPGAs Using Handel-C

In this paper, we utilize an emerging system design methodology in designing a reconfigurable HMAC-hash unit. This new methodology directly maps a design described in a high level language, Handel-C, to FPGA platforms. The Handel-C approach narrows the gap between performance and flexibility, and thus, reduces the risk of translating a high level prototype into HDLs. It provides a high degree of flexibility from two viewpoints: the language level of abstraction and the hardware reconfiguration. We consider a detailed case study: a reconfigurable HMAC-hash unit that implements six standard hash functions, MD5, SHA-1, RIPEMD-160, HMAC-MD5, HMAC-SHA-1, and HMAC-RIPEMD-160. Using Handel-C, we enhanced the performance of the designed unit by applying pipelining, parallelism, and reconfigurability. The use of Handel-C resulted in an HMAC-hash unit architecture that is better in speed than most of the previously designed units. At the same time, the area cost for putting the six standard algorithms on the same hardware core is also kept as low as possible