DocumentCode
461337
Title
Classifying Bad Chips and Ordering Test Sets
Author
Ferhani, Francois-Fabien ; McCluskey, Edward J.
Author_Institution
Center for Reliable Comput., Stanford Univ., CA
fYear
2006
fDate
Oct. 2006
Firstpage
1
Lastpage
10
Abstract
This paper shows data related to choosing a pair of test sets for digital IC production test. This data demonstrates that the choice of the second set of the pair should take into account the test metric used for the first test set. An approach for making this choice by taking defect coverage and total test length into account is presented
Keywords
integrated circuit testing; production testing; bad chips classification; digital IC production test; test sets; CMOS technology; Circuit faults; Circuit testing; Digital integrated circuits; Fault detection; Integrated circuit testing; Integrated circuit yield; Large scale integration; Production; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2006. ITC '06. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
1-4244-0292-1
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2006.297736
Filename
4079414
Link To Document