A Flexible FPGA-based Video Compression System and Its Testing Interface

This paper presents a FPGA-based video compression system (FVCS) and its testing interface system (TIS). The FVCS is designed in order to implement complex algorithms such as MPEG-4. TIS is implemented to facilitate functions´ development. A high-end FPGA from Xilinx´s Vertex-4 series has been used to perform the functions including video acquisition, compression and bit-stream transmission. FVCS implements an open architecture with a separate video lens module and can connect an optional extend memory system. Two compression solutions based on FVCS´s architecture demonstrate the flexibility