THE MODERATE-THROUGHPUT AND MEMORY-EFFICIENT LDPC DECODER

With the superior error correction capability, low-density parity-check (LDPC) codes have received much interests in the field of channel coding for 4 mobile communication, storage fields, and digital video broadcasting (DVB). In the past, parallel architecture and serial architecture decoders have been presented. In this paper, an improved serial decoder is proposed, and implemented on Altera field-programmable gate array (FPGA) device. By arranging the update scheduling elaborately, the memory overhead in decoder is reduced by 50%, and convergence speed is enhanced significantly. Moreover, an improved belief propagation (BP) algorithm is designed for the decoder. The synthesis and simulation results show that the improved serial decoder can achieve higher throughput with reduced memory overhead and superior bit error rate (BER) performance compared to serial decoder