Yield Aware Approach for Low Power Synthesis

Dual V_T along with sizing has been found to be a very effective technique for leakage power minimization in CMOS circuits. However, the use of dual-V_T not only involves higher cost of realization; it also leads to lower yield due to process parameter variations. This paper presents a novel yield-aware approach for leakage power minimization. By making more effective use of sizing, the proposed approach provides comparable reduction in leakage power by using single threshold voltage. It provides lower cost of implementation and higher yield compared to dual-V_T.