Memory Efficient LDPC Code Design for High Throughput Software Defined Radio (SDR) systems

Low-density parity-check (LDPC) codes have been adopted in the physical layer protocol of many communication systems because of their superior performance. A direct implementation of the LDPC decoder on an existing platform, such as a software defined radio (SDR), is likely to be inefficient. Our approach is to design the LDPC code in a way that takes into account the constraints imposed by the existing architecture, without compromising the communication performance. In this paper, a procedure for architecture-aware LDPC code design which minimize the number of global memory accesses in a memory constrained system is derived. The procedure is built on top of existing super-code based LDPC code design. The proposed code construction procedure also results in reduction in the number of iterations and thereby increases the throughput significantly.