DocumentCode
463743
Title
A 61MHz 72K Gates 1280??720 30FPS H.264 Intra Encoder
Author
De-Wei Li ; Chun-Wei Ku ; Chao-Chung Cheng ; Yu-Kun Lin ; Tian-Sheuan Chang
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
2
fYear
2007
fDate
15-20 April 2007
Abstract
This paper presents an HD720p 30 frames per sec H.264 intra encoder operated at 61 MHz with just 72 K gate count. We achieve the low cost and low operating frequency with the highly utilized variable pixel scheduling, and a modified three-step fast algorithm. Thus, the resulted design only needs half of operating frequency and reduces 30% of area cost compared to the previous HD720p intra encoder design.
Keywords
image resolution; video coding; H.264 intraencoder design; gate counts; three-step fast algorithm; variable pixel scheduling; Costs; Encoding; Energy consumption; Frequency; IEC standards; ISO standards; Parallel architectures; Prediction algorithms; Quantization; Video compression; H.264; Intra prediction;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech and Signal Processing, 2007. ICASSP 2007. IEEE International Conference on
Conference_Location
Honolulu, HI
ISSN
1520-6149
Print_ISBN
1-4244-0727-3
Type
conf
DOI
10.1109/ICASSP.2007.366357
Filename
4217530
Link To Document