Quasi-Resonant Interconnects: A Low Power Design Methodology

Design and analysis guidelines for resonant interconnect networks are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of the on-chip interconnect and inductor to obtain low power and low latency. Excellent agreement is shown between the proposed model and SpectraS simulations. The analysis and design of the inductance, the insertion point, and the driver resistance for minimum power consumption is described. A case study demonstrates the design of a resonant interconnect, transmitting a 5 Gbps data signal along a 5 mm line in a TSMC 0.18 mum CMOS technology. As compared to classical repeater insertion, an average reduction of 94.8% and 72.8% is obtained in power consumption and delay, respectively. As compared to optical links, a reduction of 98.5% and 60% is observed in power consumption and delay, respectively.