A Simplicial PWL Integrated Circuit Realization

Author

Di Federico, M. ; Julian, Pedro ; Poggi, T. ; Storace, M.

Author_Institution

Univ. Nacional del Sur, Bahia Blanca

fYear

2007

fDate

27-30 May 2007

Firstpage

685

Lastpage

688

Abstract

In this paper we present a mixed-signal integrated circuit in a standard CMOS 0.5 mum technology implementing a piece wise-linear (PWL) function with three inputs, where each input can be either analog or coded with 8 bits. The output of the circuit is a digital word with 8-bit precision, representing the value of the PWL function at the three-dimensional input. The circuit accesses also a 4 kB external memory, which is addressed with a 12-bit word. Experimental results are shown that demonstrate the circuit working up to 50 MHz with a maximum power consumption of 3.7 mW.

Keywords

CMOS integrated circuits; integrated circuit design; mixed analogue-digital integrated circuits; piecewise linear techniques; 0.5 micron; 12 bit; 3.7 mW; 4 kBytes; 8 bit; digital word; external memory; mixed-signal integrated circuit; piece wise-linear function; piece wise-linear integrated circuit realization; standard CMOS; Analog integrated circuits; CMOS analog integrated circuits; CMOS integrated circuits; CMOS technology; Code standards; Energy consumption; Image processing; Integrated circuit technology; Mixed analog digital integrated circuits; Piecewise linear techniques;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.377901

Filename

4252727