DocumentCode
464736
Title
Analysis of an SOC Architecture for MPEG Reconfigurable Video Coding Framework
Author
Hsiao, Jer-Min ; Tsai, Chun-Jen
Author_Institution
Dept. of Comput. Sci., Nat. Chiao Tung Univ., Hsinchu
fYear
2007
fDate
27-30 May 2007
Firstpage
761
Lastpage
764
Abstract
Due to the variety of popular video coding standards, many efforts have been put into the design of a single video decoder chip that supports multiple formats. In 2004, ISO/IEC MPEG started a new work item to facilitate multi-format video codec design and to enable more flexible usage of coding tools. The work item has turned into the MPEG reconfigurable video coding (RVC) framework. The key concept of the RVC framework is to allow flexible reconfiguration of coding tools to create different codec solutions on-the-fly. In this paper, flexible SoC architecture is proposed to support the RVC framework. Some analysis has been conducted to show the extra costs required for this platform compared to hard-wired codec architecture. In conclusion, the RVC framework can be mapped to an SoC platform to provide flexibility and scalability for dynamic application environment with reasonable cost in hardware design.
Keywords
codecs; logic design; system-on-chip; video coding; ISO/IEC MPEG; MPEG reconfigurable video coding framework; SoC architecture; codec solutions; coding tools; multiformat video codec design; single video decoder chip; system-on-chip; video coding standards; Code standards; Computer architecture; Computer science; Costs; Decoding; IEC standards; ISO standards; MPEG 4 Standard; Video codecs; Video coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.377997
Filename
4252746
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