Electrical Stress-free High Gain and High Swing Analog Buffer Using an Adaptive Biasing Scheme

Author

Dabag, Hayg ; Seo, Dongwon ; Mishra, Manu ; Hausner, Josef

Author_Institution

Inst. for Integrated Syst., Ruhr-Univ. of Bochum

fYear

2007

fDate

27-30 May 2007

Firstpage

945

Lastpage

948

Abstract

Analog circuit design techniques to avoid electrical stress are presented. A dual logic scheme and an adaptively biased common source output buffer are used to meet a reliability guideline that ensures sufficient lifetime. Both techniques are successfully used to implement an operational amplifier in a 45-nm standard CMOS process.

Keywords

CMOS integrated circuits; analogue circuits; operational amplifiers; 45 nm; CMOS process; adaptive biasing scheme; adaptively biased common source output buffer; analog buffer; analog circuit design techniques; dual logic scheme; operational amplifier; Analog circuits; CMOS technology; Diodes; Guidelines; Logic circuits; Logic devices; MOS devices; Operational amplifiers; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378082

Filename

4252792

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=464763