Design and Synthesis of a Three Input Flagged Prefix Adder

For multi-operand addition, several techniques, such as carry-save adders, Wallace, and Dadda structures based on counters and compressors have been proposed. This paper proposes a technique to accomplish three-operand addition utilizing regular adder structures such as parallel-prefix adders. One of the advantages of this technique is the elimination of dedicated adder units to perform three-input addition. Conventional prefix adders are modified to generate intermediate outputs called flag bits to allow the addition of a third arbitrary number, thereby accomplishing multi-operand addition. This adder can find its use in applications such as multiplication or multi-media units. An evaluation has been performed for 16-bit three-input flagged prefix adder architectures (TIFPA) in terms of area, delay and power. The performance of this adder design has been compared to that of carry save adders to understand the performance gain of the proposed technique.