Title :
Impact of strain on the design of low-power high-speed circuits
Author :
Ramakrishnan, H. ; Maharatna, K. ; Chattopadhyay, S. ; Yakovlev, A.
Author_Institution :
Sch. of Electr., Electron. & Comput. Eng., Newcastle Univ.
Abstract :
In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has been given on the evaluation of noise characteristics and low-power performance along with the delay characteristics under different channel straining conditions. An inverter circuit has been used for performance evaluation through simulation where the device simulator is calibrated with experimental device data. The result shows a great promise for s-Si technology in digital applications which require high throughput and low power.
Keywords :
high-speed integrated circuits; integrated circuit design; invertors; silicon; channel straining conditions; delay characteristics; inverter circuit; low-power high-speed circuits; noise characteristics; performance evaluation; s-Si devices; strained silicon devices; CMOS technology; Calibration; Capacitive sensors; Circuit simulation; Design engineering; Germanium silicon alloys; Inverters; Silicon germanium; Tensile strain; Voltage;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378254
