Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks

Key issues in wireless receivers for wireless sensor networks are discussed and existing implementations are compared. On the system level, a new method to determine power allocation is developed to ensure system requirements are met while minimizing power consumption. On the circuit level, several common designs are reevaluated in the context of low power design and the best choices for low power CMOS receiver design are given. A noise analysis shows that for extremely low power operation, the common gate LNA provides better noise performance over the commonly used common source design. Existing filters are compared and a figure of merit is used to determine the best architecture for low power design. Circuit simulations are used to show that a higher power limiting amplifier can reduce the overall receiver power for a given set of noise and gain specifications.