A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints

Hermitian codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to find a way of performing the required computations in a fast and memory efficient way so as to satisfy resource and throughput constraints imposed by the systems. The paper presents some architecture for Hermitian decoders which enhance their applicability in communication systems. Formulae and architectures for gap detection and address generation unit for satisfying memory constraints have been presented, which amount to 50% savings in storage area and 10% savings in the number of clock cycles reported in literature. A semi-parallel architecture is proposed as a solution to the latency and resource requirements tradeoff, which improves the throughput about q times compared to the word-serial architecture at an expense of some q times more adders, multipliers and simple multiplexers, where the code is defined over GF(q₂). For a t error correcting code, the resource load of the parallel architectures is about gamma(t/q + (q-3)/4)( t/q + (q-3)/4 + 1) times this architecture, where gamma is the resource requirement ratio of a multiplier and an inverter