DocumentCode
464861
Title
An Energy-efficient Reconfigurable Viterbi Decoder on a Programmable Multiprocessor
Author
Zhong, Guichang ; Willson, Alan N., Jr.
Author_Institution
Dept. of Electr. Eng., California Univ., Los Angeles, CA
fYear
2007
fDate
27-30 May 2007
Firstpage
1565
Lastpage
1568
Abstract
A reconfigurable Viterbi decoder capable of accommodating K from 6 to 9, and r = 1/2 and 1/3 has been implemented on a programmable multiprocessor, fabricated in TSMC 0.18-mum CMOS. Efficient trellis partitioning and path metric memory localization techniques endow the Viterbi decoder with simple configuration control and high efficiency. For this Viterbi decoder, performance can be traded off in favor of power savings, or vice-versa.
Keywords
CMOS digital integrated circuits; Viterbi decoding; codecs; logic partitioning; microprocessor chips; programmable circuits; trellis codes; 0.18 micron; CMOS integrated circuits; energy-efficient reconfigurable Viterbi decoder; path metric memory localization; programmable multiprocessor; trellis partitioning; Code standards; Convolutional codes; Decoding; Digital signal processing; Energy consumption; Energy efficiency; Multiaccess communication; Throughput; Viterbi algorithm; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378711
Filename
4252951
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