A High-Performance 2-D Inverse Transform Architecture for the H.264/AVC Decoder

In this paper, a high-performance 2-D inverse transform architecture for the H.264/AVC decoder is proposed. The proposed architecture utilizes the block multiplication and permutation matrices. By applying permutation matrices, the IDCT matrix is regularized and the inverse Hadamard transform is merged into IDCT with a minor modification. The proposed architecture eliminates the data transpose register array to make the 2-D direct transform possible with the minimum latency of one clock cycle. When comparing the proposed design with existing designs, the proposed design has over 22% higher throughput for computing IDCT and inverse Hadamard transform. It also owns over 62% higher hardware efficiency through the measure of DTUA for computing IDCT and inverse Hadamard transform.