FPGA Implementation of LDPC Decoders Based on Joint Row-column Decoding Algorithm

Author

He, Zhiyong ; Roy, Sébastien ; Fortier, Paul

Author_Institution

Dept. of Electr. & Comput. Eng., Laval Univ., Quebec, Que.

fYear

2007

fDate

27-30 May 2007

Firstpage

1653

Lastpage

1656

Abstract

This paper presents a joint row-column decoding algorithm for the decoding of low-density parity-check (LDPC) codes. Simulation indicates that the proposed algorithm improves the performance in both the waterfall region and the error floor region. By combining row processing with column processing, the joint row-column decoding algorithm reduces the storage requirements of extrinsic messages and avoids memory conflicts and routing congestion during the exchanges of extrinsic messages. Implementation results into field programmable gate array (FPGA) devices indicate that the proposed algorithm reduces the hardware costs by 30% and increases the decoding speed by a factor of four. A 40-parallel decoder attains a throughput of 2 Gbits/sec by using up to 20 % of the generic logic resources in a Xilinx XC4LX160 device

Keywords

codecs; field programmable gate arrays; logic design; parity check codes; FPGA implementation; LDPC decoders; Xilinx XC4LX160 device; column processing; error floor region; field programmable gate arrays; joint row-column decoding algorithm; low-density parity-check codes; parallel decoder; routing congestion; row processing; Costs; Digital video broadcasting; Field programmable gate arrays; Hardware; Helium; Iterative decoding; Parity check codes; Read-write memory; Routing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378837

Filename

4252973