DocumentCode
464914
Title
Digital Block Modeling and Substrate Noise Aware Floorplanning for Mixed Signal SOCs
Author
Kao, William H. ; Dong, Xiaopeng
Author_Institution
IC Digital Group, Cadence Design Syst., San Jose, CA
fYear
2007
fDate
27-30 May 2007
Firstpage
1935
Lastpage
1938
Abstract
In this paper the authors discuss how the problem of substrate-coupled switching noise (dI/dt and dV/dt noise) in mixed signal SOCs can be minimized or resolved by using the combined substrate analysis capabilities of SNA coupled with encounter floorplanning and placement tools. Four aspects: substrate noise modeling and injection, propagation, detection and protection were covered in the paper.
Keywords
integrated circuit layout; integrated circuit noise; mixed analogue-digital integrated circuits; system-on-chip; digital block modeling; mixed signal SOC; substrate noise aware floorplanning; switching noise; system-on-chip; Circuit noise; Clocks; Integrated circuit modeling; Integrated circuit noise; Noise figure; Noise generators; Noise level; SPICE; Signal design; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378354
Filename
4253043
Link To Document