DocumentCode
464930
Title
Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout Design
Author
Krishnamoorthy, Karthik ; Maruvada, Sarat C. ; Balasa, Florin
Author_Institution
Freescale Semicond. Inc., Phoenix, AZ
fYear
2007
fDate
27-30 May 2007
Firstpage
2032
Lastpage
2035
Abstract
This paper presents an improved topological algorithm for device-level analog placement with symmetry constraints. Based on the exploration of symmetric-feasible sequence-pairs (Balasa and Lampaert, 2000), the technique employs an efficient model of priority queue (Johnson, 1982). The use of this data structure entails a complexity of O (G middot n log log n) for each code evaluation, where n and G are the numbers of devices and symmetry groups, which is better than the complexity of other existent topological placement algorithms supporting symmetry constraints. The computation times exhibited by this approach are significantly better than those of the algorithms using an exploration strategy based on the absolute representation, as well as those of other previous topological algorithms.
Keywords
circuit optimisation; integrated circuit layout; analog layout design; device-level analog placement; multiple symmetry groups; symmetry constraints; topological placement; Analog circuits; Bismuth; Coupling circuits; Data structures; Dynamic range; Power supplies; Routing; Thermal degradation; Time factors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378437
Filename
4253067
Link To Document