A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length

This paper studies the 3D-via placement problem for 3D circuits. We model the problem in such a way that 3D-vias are assigned to layers between the circuit tiers. The placement problem consists of placing the 3D-vias with no overlap with other 3D-vias in the same layer. Positions inside the net bounding box are preferred and wire length minimization is used as target function. We present a heuristic based on the Tetris legalization approach for the 3D-via legalization. Our experimental results show that the algorithm could accommodate the 3D-vias in such a way that wire length overhead is close to zero in easy instances and still very low for harder instances (in most of the cases it is less than 0.1% and it is less than 5% in all cases). Compared to an existing approach, it obtains similar results with orders of magnitude advantage on run time.