Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems

This paper presents a dynamic reconfigurable architecture for a low-power despreader in VSF-OFCDM systems. Since the spreading factors in time and frequency domains are dependent of cell configurations, channel loads, and propagation channels, a circuit structure of the despreader is to be optimized according to these variable conditions. The proposed despreader, it is based on a dynamic reconfigurable architecture, offers optimum concurrent and pipeline processing and minimizes memory accesses using an adder network. The results show that the proposed despreader has reduced power by 13-60% compared with a basic despreader.