Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System

Author

Xu, Zhuo ; Ren, Junyan ; Wang, Xue-jing ; Ye, Fan

Author_Institution

State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai

fYear

2007

fDate

27-30 May 2007

Firstpage

2574

Lastpage

2577

Abstract

This paper presents the design of a Viterbi decoder for the multiband OFDM (MB-OFDM) ultra-wideband (UWB) communication systems. To achieve the highest data rate desired with hardware efficiency, a folded sliding block architecture is utilized. For lower data rates, some of the processing elements (PE) in the Viterbi decoder are disabled to save power. The design has been implemented on FPGA and the throughput can be up to 432 Mbps on a Xilinx Virtex-4 device.

Keywords

OFDM modulation; Viterbi decoding; block codes; codecs; field programmable gate arrays; ultra wideband communication; FPGA; MB-OFDM UWB communication system; folded sliding block Viterbi decoders; folded sliding block architecture; multiband OFDM ultra wideband communication systems; processing elements; Application specific integrated circuits; Convolutional codes; Field programmable gate arrays; Hardware; Iterative decoding; OFDM; Throughput; Ultra wideband communication; Ultra wideband technology; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.377841

Filename

4253203