Title :
Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories
Author :
Blum, Daniel R. ; Delgado-Frias, José G.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA
Abstract :
We present a novel MBU-tolerant design, which utilizes layout-based interleaving and multiple-node disruption tolerant memory latches. This approach protects against grazing incidence particle strikes, which produce disruptions with the widest possible spatial separation. Advantages with respect to size, complexity, and MBU tolerance are realized when this approach is compared to existing solutions.
Keywords :
flip-flops; integrated memory circuits; memory architecture; layout-based interleaving; memory latches; multiple-bit upset tolerant static memories; multiple-node disruption tolerant; spatial separation; Error correction codes; Integrated circuit layout; Interleaved codes; Latches; Logic; Particle scattering; Protection; Redundancy; Robustness; Single event upset;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378631
