• DocumentCode
    465042
  • Title

    Architecture for Multiple Reference Frame Variable Block Size Motion Estimation

  • Author

    Warrington, Stephen ; Sudharsanan, Subramania ; Chan, Wai-Yip

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Queen´´s Univ.
  • fYear
    2007
  • fDate
    27-30 May 2007
  • Firstpage
    2894
  • Lastpage
    2897
  • Abstract
    This paper proposes a high throughput variable block size motion estimation (VBSME) architecture supporting multiple reference frames (MRF). To enable best rate-distortion performance for different video contents, the architecture allows selection between high spatial resolution motion search over a single reference frame, or MRF search at a lower spatial resolution. Through synthesis of an ASIC implementation, the architecture is shown to be suitable for high definition video resolutions and frame rates. The architecture also provides a higher overall macroblock throughput than other VBSME architectures in the literature.
  • Keywords
    application specific integrated circuits; image sequences; motion estimation; rate distortion theory; ASIC implementation; frame rates; high definition video resolutions; multiple reference frame; rate-distortion performance; variable block size motion estimation; video contents; Application specific integrated circuits; Automatic voltage control; Computer architecture; Hardware; High definition video; Motion estimation; Rate-distortion; Spatial resolution; Throughput; Tiles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
  • Conference_Location
    New Orleans, LA
  • Print_ISBN
    1-4244-0920-9
  • Electronic_ISBN
    1-4244-0921-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2007.377854
  • Filename
    4253283