Memory Cache Based Motion Compensation Architecture for HDTV H.264/AVC Decoder

In this paper, we present a high performance memory cache based motion compensation architecture for H.264/AVC HDTV decoder. To solve the bottleneck of memory bandwidth for H.264/AVC HD applications, three combined bandwidth optimization strategies are proposed to minimize the memory bandwidth for MB-based decoding. To improve the interpolation hardware utilization and reduce the interpolation cycles, an interpolation classification scheme is proposed. By classifying the fifteen fractional pixels into five types and processed correspondingly, the interpolation cycles decrease significantly. A direct mapping memory cache characterized with circular addressing, byte-aligned addressing and horizontal and vertical parallel access is designed to support the proposed scheme. Averagely 60-80% reduced memory bandwidth can be offered and the interpolation hardware can be fully utilized and interpolate one MB within 304 cycles, which can satisfy the real time constraint for H.264/AVC HD (1920times1088) 30fps decoder with 32K logic gates, operating at 100MHz.