A Nonlinear Model for Phase Noise and Jitter in LC Oscillators

In the presence of high-power environmental noise, such as that present in the common substrate and on the power and ground (P/G) rails of a system-on-a-chip (SOC), the current-to-phase relationship for an LC oscillator cannot be assumed linear. This paper presents a simple nonlinear modification to the well-established linear time-variant (LTV) model for phase noise that facilitates a more accurate prediction of oscillator phase noise and jitter in the presence of high-power noise. For low-power noise, this nonlinear model simplifies to the LTV metric. The accuracy of the proposed analytical model is verified through the simulation of a 10 GHz Colpitts oscillator in a 0.18mum CMOS process.