Title :
A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range
Author :
Gundel, Adnan ; Carr, William N.
Author_Institution :
New Jersey Inst. of Technol., Newark, NJ
Abstract :
This paper describes the design of a CMOS PLL clock synthesizer targeting biomedical applications in the 20-400 MHz range. Based on integer-N architecture, the synthesizer produces a 400-mV LVDS output signal swing on a 1.2 V common mode level under 50-Omega load. Fabricated in a 0.35-mum N-well CMOS process technology, the PLL achieves a period jitter of 6.5-psrms and 38-pspp at 216 MHz with a phase noise of -120 dBc/Hz at frequency offsets above 10 KHz. The phase noise response has a peak of -115 dBc/Hz at the loop bandwidth.
Keywords :
CMOS integrated circuits; clocks; frequency synthesizers; jitter; phase locked loops; 0.35 micron; 1.2 V; 20 to 400 MHz; 400 mV; 50 ohm; CMOS PLL clock synthesizer; N-well CMOS process technology; biomedical applications; common mode level; integer-N architecture; low jitter; Bandwidth; Charge pumps; Clocks; Jitter; Phase frequency detector; Phase locked loops; Phase noise; Ring oscillators; Synthesizers; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378067
