High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique

This paper presents an efficient low power protection technique for thin gate oxide of DMOS transistors. By connecting a capacitive divider structure to the floating gate node of a DMOS transistor, its effective gate oxide thickness is increased, and a protection from breakdown due to high voltages (HV) applied to its gate is achieved. Several HV circuits, including: positive voltage doubler and level-up shifter suitable for ultrasound sensing systems are built successfully around this technique. These circuits were implemented with the 0.8 mum CMOS/DMOS HV DALSA process. Experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 120V.